The present invention relates to an inverter circuit, and more specifically to a particular inverter circuit of the type comprised of field effect transistors and bipolar transistors featuring high speed operation and low power consumption.
FIG. 1 shows a conventional inverter circuit comprised of MOS transistors and NPN transistors, which have been generally used to provide high speed performance. In FIG. 1, the circuit is comprised of a PMOS transistor 3, N-channel MOS transistors 4, 5, and 6 and NPN transistors 7 and 8. The NPN transistor 7 has a collector C connected to a power source terminal 9, an emitter E connected to an output terminal 2 and a base B connected to a drain D of the PMOS transistor 3. The other NPN transistor 8 has a collector C connected to the output terminal 2 and to a drain D of the NMOS transistor 5, a base B connected to a source S of the N-channel MOS transistor 5, and an emitter E connected to the ground. The N-channel MOS transistor 4 has a drain D connected to the drain D of the P-channel MOS transistor 3 and to the base B of the NPN transistor 7, and a source S connected to the ground. Further, the N-channel MOS transistor 6 has a drain D connected to the source S of the N-channel MOS transistor 5 and to the base B of the NPN transistor 8, and a source S connected to the ground. The N-channel MOS transistor 4 operates when the P-channel MOS transistor 3 turns off and the NMOS transistor 5 turns on to draw electric charge stored in the base of the NPN transistor 7 to thereby switch the NPN transistor 7 to the OFF-state. On the other hand, the N-channel MOS transistor 6 operates when the PMOS transistor 3 turns on and the N-channel MOS transistor 5 turns off to draw electric charge stored in the base of the NPN transistor 8 to thereby switch the NPN transistor 8 to the OFF-state.
The FIG. 1, the inverter circuit has the following drawbacks with respect to the NMOS transistor 4. Firstly, since the gate of the N-channel MOS transistor 4 is connected to an input terminal 1 as well as the P-channel MOS transistor 3 and N-channel MOS transistor 5 those of which drive the NPN transistors 7 and 8, respectively, an input capacitance is unavoidably increased. Next, when the N-channel MOS transistor 4 turns on to draw base charge from the NPN transistor 7, there may be caused possibility that the NPN transistor 7 is transiently and excessively reverse-biased between the base and emitter. If the reverse-biasing exceeds the emitter-base withstanding voltage, hot carriers are generated due to avalanche multiplication. Consequently, electric charge may be stored in the SiO.sub.2 region which contacts with a depletion layer between the base and emitter, or interface-state of an interface between Si and SiO.sub.2 regions may be increased to thereby lower h.sub.FE of the bipolar transistor to cause reliability problem. On the other hand, in order to eliminate the above noted drawbacks, a gate width of the NMOS transistor 4 could be reduced; however, such arrangement would cause another problem. Namely, it takes a longer time to draw the base charge of the NPN transistor 7 thereby impairing the operation speed of the circuit. In addition, the inverter circuit of FIG. 1 is basically composed of six elements, the number of which is greater than that of another type of the conventional inverter of FIG. 2 composed of a CMOS having two elements, thereby causing drawback shaped with that of the circuit of FIG. 1, which is a large area on an integrated circuit device.